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Lemniscale

Welcome to lemniscale, the advanced Technology Company paving the way to the future. We are a team of like-minded and determined individuals, all sharing a vision for success. We believe that our sophisticated technology has the potential to become an industry sensation. Would you like to find out more? Explore our website today.

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What We Do

At lemniscale, we believe that our solutions will soon become one of the biggest segments in the industry. We’ve only just started, but we already know that every product we build requires hard-earned skills, dedication and a daring attitude. Continue reading and learn all there is to know about the smart tech behind our successful Technology Company.

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 Design Verification Services

Job Title

We provide ASIC Verification Services including

  • Architecting and Developing block level verification environments for sub-system and fullchip using SystemVerilog and UVM methodology.

  • Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology

  •  Integration/development of C tests/APIs and SW build flow and UVM mailboxes and HW/SW communication components and of   lower level UVM testbenches.

  • Test plan development.

  •  Power Aware testbench development and simulations

  • Seamless porting between simulation/emulation/prototyping platforms

  • Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

  • Coverage collection and closure

  • Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

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Trainings

ASIC FrontEnd Verification course

  • A verification engineer define verification process by  developing/ integrating UVCs or VIPs  to determine whether design code works as expected before it is send to backend process.

  • A verification engineer develops checkers in order to validate protocol intent of the Design.

  • A verification engineer work on debugging a design simulations and  modifications might be recommended to tweak the design.

  • Verification engineer is responsible for coverage closure by implementing coverage model.


course curriculum:

HDLs: Verilog

HVLs : SystemVerilog 

  •         Datatypes, Oops, Interfaces, Functional Coverage, Assertions, Interprocess communications etc             

Methodology: OVM/UVM 

      Factory, TLM, UVC Development, Virtual Sequencer, Virtual Sequence, Creating Test Scenarios 
Scripting : PERL/Python 

Projects :  Industry Standards protocols like Ethernet/AMBA
Duration : 5 Months Training + 2 Months Internship  

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Our Business

lemniscale is a leading provider of cutting-edge technologies and services, offering scalable solutions for companies of all sizes. Founded by a group of friends who started by scribbling their ideas on a piece of paper, today we offer smart, innovative services to dozens of clients worldwide.

We built our solutions by closely listening to our potential clientele and understanding their expectations with our product. We know how to analyze this information and customize our offering to changing market needs. Why not join our fast growing customer base? Get in touch today to learn more about the lemniscale story.

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"The secret of getting ahead is getting started"

Mark Twain

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Bangalore

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